Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test

ABSTRACT

An integrated circuit ( 1600 ) includes a debug module ( 1602 ) and a clock generator ( 1610 ). The debug module ( 1602 ) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator ( 1610 ) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator ( 1610 ) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is related to co-pending U.S. patent application Ser. No. ______ (Attorney Docket No. TT6313), entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT” filed on May 17, 2007, by Craig Eaton et al., U.S. patent application Ser. No. ______ (Attorney Docket No. TT6314), entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT USING PULSE SKIPPING” filed on May 17, 2007, by Bill K. C. Kwan, U.S. patent application Ser. No. ______ (Attorney Docket No. TT6315), entitled “TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT USING MULTIPLE CLOCK GENERATORS” filed on May 17, 2007, by Craig Eaton et al., all of which are incorporated herein by reference in their entirety.

BACKGROUND

1. Field of the Disclosure

The present disclosure is generally directed to clock signal manipulation and, more particularly, to techniques for integrated circuit clock signal manipulation to facilitate functional and speed test.

2. Description of the Related Art

Traditionally, power management of computer systems has been implemented by adjusting a system clock frequency (and frequently an associated voltage of a system clock) to achieve optimal (or near optimal) power savings at a given performance level. Typically, the system clock frequency has been adjusted by changing a frequency of a phase locked loop (PLL), which has provided the system clock. Moreover, during functional and speed test of an integrated circuit (IC) it is relatively common to manipulate one or more clock signals associated with the IC to confirm that the IC properly functions under a number of different conditions or in an attempt to verify in what clock cycle a failure occurs. In a typical case, clock signals, such as system clocks, have been manipulated by adjusting a frequency of an associated PLL. Unfortunately, when a frequency of a PLL is adjusted there may be a latency of several hundred microseconds before the PLL re-locks and the system can resume normal operation. In processor systems that employ multiple PLLs, each of which provide respective clock signals for various subsystems, the system latency may assume the latency of the PLL with the greatest re-locking latency. Moreover, in systems employing multiple PLLs, synchronization of respective clock signals provided by the PLLs may require relatively sophisticated design solutions.

Traditionally, power management of computer systems has been facilitated by a number of different techniques. For example, legacy computer systems have implemented advanced power management (APM) compliant designs that employed operating system (OS) control of power management, via a basic input output system (BIOS). Today, most computer systems employ advanced configuration and power interface (ACPI) compliant designs to facilitate power management. The ACPI specification provides for OS control of system power management via a BIOS, which provides the OS with methods for directly controlling low-level hardware details, such that the OS has nearly complete control over power savings. In general, the ACPI specification facilitated the introduction of power management features, which were previously only available in portable computers, to desktop computers and servers. For example, a computer system may be put into extremely low-energy states from which ordinary interrupts can quickly wake the system.

The ACPI specification defines seven states (G0, G1-S1, G1-S2, G1-S3, G1-S4, G2, and G3) for an ACPI-compliant computer system. The G0 state is the normal working state of the computer system. In the G0 state a central processing unit (CPU) may execute instructions or repeatedly transition into and out of low-energy states, e.g., C0-Cn and D0-D3. For example, laptop computer systems routinely power down all currently unused devices when battery-powered. The G1 state is subdivided into four sleep modes S1 through S4. The time needed to bring the system from state G1 to state G0 is shortest for the S1 mode, which is the most power-hungry of the sleep modes. The G2 state is almost the same as the G3 state (mechanical off), but in the G2 state some components remain powered so the computer can “wake” in response to input from a keyboard, a local area network (LAN) device, or a universal serial bus (USB) device, etc. The G2 state is typically initiated by the OS in response to a user issued shut-down command. The device states D0-D3 are device dependent. In the D0 state, the device is in a fully-on operating state. The D1 and D2 states are intermediate power states whose definition varies by device. In the D3 state, the device is powered off and is unresponsive.

The ACPI specification defines four central processing unit (CPU) power states, i.e., C0-C3. The C0 state is the CPU operating state. The C1 state is where the CPU is not executing instructions, but can return to an executing state essentially instantaneously. The C2 state is a state where the CPU maintains all software visible state, but may take longer to wake-up. In the C3 state, the CPU does not need to keep its cache coherent, but otherwise maintains CPU state. The ACPI specification defines sixteen performance (P) states that a device or CPU (operating in D0 or C0, respectively) can enter. While the P states are implementation dependent, P0 is always the highest-performance state, with P1 to Pn being successively lower-performance states, up to an implementation-specific limit of n, which is less than or equal to sixteen.

With reference to FIG. 1, a conventional phase locked loop (PLL) 100 is illustrated that provides an application appropriate output clock signal at a frequency that is responsive to a reference clock signal and one or more associated divider values. The reference clock signal is provided to an input of an input divider 102 of the PLL 100. A divider value of the input divider 102 is dictated by a value stored in an input divider register 104. An output of the input divider 102 is coupled to a first input of a phase detector 106, whose output is coupled to an input of a loop filter 108. An output of the loop filter 108 is coupled to an input of a charge pump 110, whose output is coupled to an input of a voltage controlled oscillator (VCO) 112. An output of the VCO 112 is coupled to an input of a feedback divider 114, whose output is coupled to a second input of the phase detector 106. A divider value of the feedback divider 114 is dictated by a value stored in a feedback divider register 116.

With reference to FIG. 2, a conventional processor system 200 is illustrated that includes a single PLL 202, which may be configured in the same manner as the PLL 100 of FIG. 1. The PLL 202 is coupled to a power management state controller 204, which is configured to write values to one or more registers, e.g., input and feedback divider registers, of the PLL 202 to cause the PLL 202 to provide a CPU clock signal to CPU 206 at a desired frequency for a given power state.

Moving to FIG. 3, a conventional processor system 300 is illustrated that employs multiple PLLs. A main PLL 302 receives a reference clock signal and provides an output clock signal (having a desired frequency) to inputs of PLL 304 and PLL 306, respectively. The PLL 304 provides a CPU clock signal to CPU 310 and the PLL 306 provides a clock signal to circuit 312, which may be a CPU or other circuit which requires a clock signal. The PLLs 304 and 306 may provide a clock signal at the same or different frequencies. The PLLs 302, 304 and 306 are coupled to a power management state controller 308, which is configured to write values to registers, e.g., input and feedback divider registers, of the PLLs 302-306 to cause the PLLs 304 and 306 to provide clock signals at one or more desired frequencies corresponding to desired power states. It should be appreciated that when the frequencies of the clock signals provided by the PLLs 302-306 are changed at the same time, latency associated with the frequency change corresponds to a re-locking time of the slowest one of the PLLs 302-306.

What is needed are clock signal manipulation techniques that facilitate functional and speed test of an integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 is an electrical block diagram of a conventional phase locked loop (PLL).

FIG. 2 is an electrical block diagram of a conventional processor system that employs a single PLL.

FIG. 3 is an electrical block diagram of a conventional processor system that employs multiple PLLs.

FIG. 4 is an electrical block diagram of a processor system that employs a single PLL in conjunction with multiple clock generators, configured according to various embodiments of the present disclosure.

FIG. 5 is an electrical block diagram of a processor system that employs a clock generator system that includes a clock state machine and multiple clock generators, configured according to various aspects of the present disclosure.

FIG. 6 is an electrical block diagram of an example clock generator, configured according to an embodiment of the present disclosure.

FIG. 7 is a signal diagram of example quadrature clock signals (CLK_0 and CLK_90) that are generated from a reference clock signal (REFCLK) and provided to respective clock inputs of the clock generator of FIG. 6.

FIG. 8 is an electrical block diagram of an example clock generator (edge selection circuit) that utilizes the quadrature clock signals (CLK_0 and CLK_90) illustrated in FIG. 7.

FIG. 9 is an example signal diagram of various signals associated with the clock generator of FIG. 6.

FIG. 10 is an example signal diagram of quadrature clock signals (CLK_0 and CLK_90) that are provided to clock inputs of the clock generator of FIG. 6 and three example generated clock signals (GEN_CLK) provided at an output of the clock generator of FIG. 6.

FIG. 11 is a flow chart of an example process for providing a generated clock signal responsive to quadrature clock signals and a mode signal.

FIG. 12 is a signal diagram that depicts relationships between various signals that may be associated with a processor subsystem, configured according to the present disclosure, under test.

FIG. 13 is a signal diagram that depicts an unmodified generated clock signal (‘1100’) contrasted with a modified generated clock signal (‘1000’) with a shrunk high-phase and a corresponding stretched low-phase in two quadrature clock cycles.

FIG. 14 is a signal diagram that depicts an unmodified generated clock signal (‘11001100’) contrasted with modified clock signal (‘1010000’) with a shrunk high-phase, a shrunk low-phase and a stretched low-phase in four quadrature clock cycles.

FIG. 15 is a signal diagram that depicts an unmodified generated clock signal (‘1100’) contrasted with modified generated clock signal (‘1110’) with a stretched high-phase and a shrunk low-phase in two quadrature clock cycles.

FIG. 16 is an electrical block diagram of an integrated circuit that includes a debug module and a clock generator, which are configured according to one or more embodiments of the present disclosure.

The use of the same reference symbols in different drawings indicates similar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

According to various embodiments of the present disclosure, a programmable clock generator is described herein that provides a generated clock signal having a relatively wide frequency range. The clock generator is configured to facilitate a frequency change in the generated clock signal (responsive to a mode signal) without requiring modification of a frequency of a clock signal (e.g., quadrature clock signals) provided by a phase locked loop (PLL) associated with the clock generator. The clock generator technique is particularly advantageous when employed in modern microprocessor systems that employ multiple clock domains, each of which may operate at a different frequency and may frequently change frequency in response to, for example, a power management state change. In this case, multiple clock generators (e.g., one for each clock domain) may be employed to facilitate independent and frequent change in operating frequencies of the clock domains.

According to one aspect of the present disclosure, a pulse removal technique may be employed to provide increased adjustment of an effective frequency of a generated clock signal. According to this embodiment, the effective frequency of the generated clock signal is modified by periodic pulse skipping (i.e., removing one or more clock pulses from each selected time period in a clock stream of the generated clock signal). According to various aspects of the present disclosure, a single PLL may be used to provide quadrature clock signals for a number of clock generators, which do not include internal PLLs. The clock generators may provide respective generated clock signals at different frequencies to associated clocked logic circuits. The associated clocked logic circuits may correspond to one or more CPU cores, a Northbridge circuit, a memory block, etc. When a clock generator is providing a generated clock signal to a static clocked logic circuit, the clock generator may employ periodic pulse skipping, i.e., removing one or more pulses from a clock stream during each predetermined time period of the clock stream. According to various aspects of the present disclosure, a clock generator may be designed to provide generated clock signals with high frequency granularity and frequencies that cannot be readily provided by conventional clock dividers. As used herein, the term “coupled” includes both a direct electrical connection between elements (or blocks) and an indirect electrical connection between elements (or blocks) provided by one or more intervening elements (or blocks). The term “actual frequency,” as used herein, means a frequency achieved without employing pulse skipping. As used herein the term “effective frequency” means a frequency achieved with pulse skipping or achieved without employing pulse skipping. In this disclosure, “pulse skipping” means removing one or more pulses from a clock stream within a predetermined time period.

While a conventional flip-flop based counter frequency divider can be used to provide a generated clock signal, a conventional flip-flop based counter frequency divider is not readily configurable to provide arbitrary clock signal waveforms and can usually only toggle on a rising edge of a reference clock signal. As such, generating a clock signal at a frequency with a conventional flip-flop base counter frequency divider has required a reference clock signal having a frequency that is four times the frequency required to generate the same frequency clock signal using a clock generator configured according to the present disclosure. Moreover, conventional flip-flop based counter frequency dividers are not capable of generating a divide by one or a divide by one-half. While a conventional shift register may function as a clock generator to generate arbitrary clock signal waveforms, conventional shift registers have also required a reference clock signal having a frequency that is four times the generated clock signal frequency required to generate the same frequency clock signal using a clock generator configured according to the present disclosure. In high frequency applications, generating a reference clock signal at a frequency that is four times a generated clock signal may consume a relatively large amount of power and may be impractical.

According to one aspect of the present disclosure, a technique of operating an integrated circuit includes receiving a test pattern and providing a mode signal based on the test pattern. A first clock signal, a second clock signal, and the mode signal are received. The first and second clock signals are out of phase and have the same clock frequency. A generated clock signal is provided whose effective frequency is based on the first and second clock signals and the mode signal.

According to another embodiment of the present disclosure, an integrated circuit includes a debug module and a clock generator. The debug module is configured to receive a test pattern and provide a mode signal, based on the test pattern. The clock generator includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

According to another aspect of the present disclosure, a processor includes a central processing unit having a clock input, a register configured to receive a test pattern, a mode signal generator, and a clock generator. The mode signal generator is coupled to the register and is configured to provide a mode signal, based on the test pattern. The clock generator is configured to receive a first clock signal, a second clock signal, and the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator is configured to provide a generated clock signal to the clock input of the central processing unit. The generated clock signal has an effective frequency that is based on the first and second clock signals and the mode signal, which is configured to cause at least one of a selected high-phase and a selected low-phase of the generated clock signal to be shrunk.

With reference to FIG. 4, an example processor system 400 is illustrated that includes two clock generators 404 and 406 that are configured according to various aspects of the present disclosure. The clock generators 404 and 406 receive quadrature clock signals from a phase locked loop (PLL) 402 that receives a reference clock signal from, for example, a crystal oscillator. The clock generators 404 and 406 are configured to generate clock signals that can rise (or fall) responsive to each clock edge of the quadrature clock signals. As is described in further detail below, the clock generators 404 and 406 facilitate modification of a frequency of clock signals provided from the generators 404 and 406 without changing input and feedback dividers of the PLL 402. In this manner, latency associated with re-locking the PLL 402 at frequency change is essentially avoided. Moreover, frequencies of the clock signals provided by the generators 404 and 406 may be independently changed in a relatively efficient manner. In at least one embodiment, when a frequency of a clock signal is changed the frequency is changed incrementally to reduce inductive noise that may be generated. While only two clock generators are shown in FIG. 4, it should be appreciated that any number of clock generators, e.g., one for each clock domain, may be employed in a system configured according to one or more of the disclosed embodiments.

As is illustrated, the generator 404 provides a generated clock signal (GEN_CLK1) to CPU 408. Similarly, the generator 406 provides a generated clock signal (GEN_CLK2) to CPU 410. The generators 404 and 406 are coupled to a power management module (e.g., a power management state controller) 412, which provides information to a sequential logic circuit (not shown in FIG. 4) that the sequential logic circuit (e.g., a clock state machine) utilizes to provide respective patterns (of enable or mode bits) to the generators 404 and 406, which the generators 404 and 406 use to generate the respective generated clock signals at desired frequencies. It should be appreciated that the frequencies of the generated clock signals may be changed, according to the various techniques disclosed herein, in response to events other than power management events. It should also be appreciated that while the discussion herein focuses on using quadrature clock signals in conjunction with the generators 404 and 406 the techniques described herein may be broadly extended to clock generators that use multiple clock signals that have an established phase relationship to provide generated clock signals having desired frequencies. For example, four clock signals with a progressive forty-five degree phase relationship (i.e., a first clock signal at zero degrees, a second clock signal at forty-five degrees, a third clock signal at ninety degrees, and a fourth clock signal at one-hundred thirty-five degrees) may be used to provide eight clock edges each clock cycle.

Moving to FIG. 5, a processor system 500 is illustrated that employs a clock generator system that uses a single PLL 502 to provide generated clock signals (GCLK0, GCLK1, NCLK, and NCLK2X) to multiple processor subsystems 506, 508, 510, and 512. In FIG. 5, the processors subsystems 506, 508, 510, and 512 correspond to a first processor core (core 0), a second processor core (core 1), a Northbridge (NB), and a memory module (DDR2), respectively. It should be appreciated that the techniques disclosed herein may be readily extended to processor systems that included more or less than two cores. The processor system 500 includes a clock state machine 514 and multiple clock generators 520, 522, 524, and 526, which are each configured according to various embodiments of the present disclosure to provide the generated clock signals (GCLK0, GCLK1, NCLK, and NCLK2X) at the same or different frequencies. Responsive to input received from a power management module (which may be implemented in the Northbridge) or other subsystem, the clock state machine 514 provides an appropriate pattern to each of the clock generators 520-526. In a typical implementation, the clock state machine 514 includes a separate state machine (to respectively generate an appropriate pattern) for each of the clock generators 520-526. To reduce overhead associated with providing patterns to the clock generators 520 and 522, two enable bits per quadrature clock cycle my be employed. In this case, each of the two bits is provided to two inputs of each of the clock generators 520 and 522. It should be appreciated that only providing two enable bits per quadrature clock cycle reduces the resolution of the frequencies of the generated clock signals that may be provided.

Moving to FIG. 6, a clock generator 600 is depicted that includes eight flip-flops 602, eight flip-flops 604, eight flip-flops 606, and eight flip-flops 608. The flip-flops 602-608 may be, for example, edge-triggered D flip-flops or flow-through latches. In the clock generator 600 of FIG. 6, new patterns are provided to data inputs of the flip-flops 602-608 every eight processor cycles of the clock signal CLK_0. Providing new patterns (e.g., two or four bit patterns) every eight quadrature clock cycles reduces a required complexity of a state machine (or other logic circuit) that generates the patterns, which correspond to a desired frequency for a clocked device. It should be appreciated that, depending on the application, a state machine may be designed to produce new patterns each quadrature clock cycle, if desired. Respective outputs of the flip-flops 602 are provided to respective data inputs of a multiplexer 610, whose output is coupled to a first data input (EN_0) of edge selection circuit 622. Similarly, respective outputs of the flip-flops 604 are provided to respective data inputs of multiplexer 612, whose output is coupled to a second data input (EN_90) of the edge selection circuit 622. In a similar manner, respective outputs of the flip-flops 606 are provided to respective data inputs of multiplexer 614, whose output is coupled to a third data input (EN_180) of the edge selection circuit 622. Likewise, respective outputs of the flip-flops 608 are provided to respective data inputs of multiplexer 616, whose output is coupled to a fourth data input (EN_270) of the edge selection circuit 622.

The edge selection circuit 622, based on the quadrature clock signals (CLK_0 and CLK_90) alternately selects a mode (enable) bit at the first, second, third, and fourth inputs to set a frequency of a generated clock signal (GEN_CLK). For example, assuming that the quadrature clock signals are set at a frequency of 2.0 GHz and a pattern of ‘1010’ is applied to the first, second, third, and fourth inputs, respectively, of the edge selection circuit 622 each quadrature clock cycle, a 4.0 GHz generated clock signal (GEN_CLK) is provided at the output of the edge selection circuit 622 (see FIG. 10). As another example, assuming that the quadrature clock signals are set at a frequency of 2.0 GHz and a pattern of ‘1100’ is applied to the first, second, third, and fourth inputs, respectively, of the edge selection circuit 622 each quadrature clock cycle, a 2.0 GHz generated clock signal (GEN_CLK) is provided at the output of the edge selection circuit 622 (see FIG. 10). As yet another example, assuming that the quadrature clock signals are set at a frequency of 2.0 GHz and a pattern of ‘1101’ is applied to the first, second, third, and fourth inputs, respectively, of the edge selection circuit 622 for a first quadrature clock cycle, a pattern of “1011” is applied to the first, second, third, and fourth inputs, respectively, of the edge selection circuit 622 for a second quadrature clock cycle, and a pattern of “0110” is applied to the first, second, third, and fourth inputs, respectively, of the edge selection circuit 622 for a third quadrature clock cycle, a 2.667 GHz generated clock signal (GEN_CLK) is provided at the output of the edge selection circuit 622 (see FIG. 10). Example patterns for divider values of 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2, and 2.25 are set forth below in TABLE 1 for quadrature clock signals having a frequency of 2.0 GHz.

TABLE 1 Divider 0.5 0.75 1 1.25 1.5 1.75 2 2.25 Output 4000 2667 2000 1600 1333 1143 1000 889 Frequency (Mhz) Pattern   2   3   4   5   6   7   8  9 length (bits) Clock 10 110 1100 11100 111000 1111000 11110000 111110000 Waveform # Cycles to   1   3   1   5   3   7   2  9 repeat Cycle 0 1010 1101 1100 1110 1110 1111 1111 1111 Inputs Cycle 1 Repeat 1011 Repeat 0111 0011 0001 0000 1000 Inputs Cycle 2 0110 0011 1000 1110 Repeat 0111 Inputs Cycle 3 Repeat 1001 Repeat 0011 1100 Inputs Cycle 4 1100 1100 0011 Inputs Cycle 5 Repeat 0111 1110 Inputs Cycle 6 1000 0001 Inputs Cycle 7 Repeat 1111 Inputs Cycle 8 0000 Inputs Cycle 9 Repeat Inputs

Example patterns for divider values of 2.5, 2.75, 3, and 3.25 are set forth below in TABLE 2 for quadrature clock signals having a frequency of 2.0 GHz.

TABLE 2 Divider 2.5 2.75 3 3.25 Output Frequency (Mhz) 800 727 667 615 Pattern length (bits)  10  11  12  13 Clock Waveform 1111100000 11111100000 111111000000 1111111000000 # Cycles to repeat  5  11  3  13 Cycle 0 Inputs 1111 1111 1111 1111 Cycle 1 Inputs 1000 1100 1100 1110 Cycle 2 Inputs 0011 0001 0000 0000 Cycle 3 Inputs 1110 1111 Repeat 0111 Cycle 4 Inputs 0000 1000 1111 Cycle 5 Inputs Repeat 0011 0000 Cycle 6 Inputs 1111 0011 Cycle 7 Inputs 0000 1111 Cycle 8 Inputs 0111 1000 Cycle 9 Inputs 1110 0001 Cycle 10 Inputs 0000 1111 Cycle 11 Inputs Repeat 1100 Cycle 12 Inputs 0000 Cycle 13 Inputs Repeat

Example patterns for divider values of 3.5, 3.75 and 4 are set forth below in TABLE 3 for quadrature clock signals having a frequency of 2.0 GHz.

TABLE 3 Divider 3.5 3.75 4 Output Frequency (Mhz) 571 533 500 Pattern length (bits)  14  15  16 Clock Waveform 11111110000000 111111110000000 1111111100000000 # Cycles to repeat  7  15  4 Cycle 0 Inputs 1111 1111 1111 Cycle 1 Inputs 1110 1111 1111 Cycle 2 Inputs 0000 0000 0000 Cycle 3 Inputs 0011 0001 0000 Cycle 4 Inputs 1111 1111 Repeat Cycle 5 Inputs 1000 1110 Cycle 6 Inputs 0000 0000 Cycle 7 Inputs Repeat 0011 Cycle 8 Inputs 1111 Cycle 9 Inputs 1100 Cycle 10 Inputs 0000 Cycle 11 Inputs 0111 Cycle 12 Inputs 1111 Cycle 13 Inputs 1000 Cycle 14 Inputs 0000 Cycle 15 Inputs Repeat

In TABLES 1-3, the pattern length is the length of the repeating clock waveform measured in quadrature clock phases. For example, to generate a 2 GHz clock signal a pattern with a length of four and a value of “1100” is provided in each quadrature clock cycle. As another example, to generate a 1.333 GHz clock signal a pattern with a length of six and a value of “111000” is repeated two times over three quadrature clock cycles.

Turning to FIG. 8, the edge selection circuit 622 (clock generator) is illustrated in further detail. The circuit 622 includes a flip-flop 804, a flip-flop 806, a flip-flop 808, and a flip-flop 810. The flip-flops 804-810 may be, for example, edge-triggered D flip-flops or flow-through latches. Patterns may be provided to respective data inputs of the flip-flops 804-810, via the flip-flops 602-608 of FIG. 6. Alternatively, patterns may be directly provided to the data inputs of the flip-flops 804-810. Clock inputs of the flip-flops 804 and 806 receive an inverted CLK_0 signal, provided by inverter 802. An output of the flip-flop 804 is coupled to a first data input (0) of multiplexer 812 and an output of the flip-flop 806 is coupled to a second data input (1) of multiplexer 812. Similarly, an output of the flip-flop 808 is coupled to a third data input (2) of multiplexer 812 and an output of the flip-flop 810 is coupled to a fourth data input (3) of multiplexer 812. The multiplexer 812, based on edges of the quadrature clock signals (CLK_0 and CLK_90), alternately selects an enable bit at the first, second, third, and fourth inputs, respectively, of the multiplexer 812 to set a frequency of a generated clock signal (GEN_CLK).

The edge selection circuit 622 reads four bits in parallel each quadrature clock cycle (includes four clock edges) and serially reads them out as the generated clock signal (GEN_CLK). The data inputs of the flip-flops 804-810 form a 4-bit pattern register. The outputs of the flip-flops 804-810 feed the data inputs of the 4:1 multiplexer 812. The quadrature clock signals (CLK_0 and CLK_90) feed respective select inputs of the multiplexer 812, which selects the proper pattern bit for each quadrature clock cycle. As the output of each flip-flop 804-810 is setup to a respective one of the data inputs of the multiplexer 812 before the data inputs are selected, the clock-to-output delay of the circuit 622 is substantially insensitive to the delay of the flip-flops 802-81 0 and is substantially dependent on the select-to-output delay of the multiplexer 812. When the pattern registers are supplied by a clock domain running at one-eighth the frequency of the quadrature clock signals, logic that generates the pattern register bits may be simplified. In one embodiment, external logic (e.g., a state machine) supplies the pattern register bits thirty-two bits at a time, four bits for each of the eight quadrature clock cycles. A 3-bit counter 620 (see FIG. 6), which generates a divide-by-eight clock (DIV8_CLK), is used to select which four pattern bits are consumed each quadrature clock cycle.

According to another aspect of the present disclosure a pulse removal technique may be employed to adjust a frequency of a generated clock signal. Removing pulses from a clock stream provides a generated clock signal having an effective frequency that may be used to clock static clocked logic circuits, such as CPUs. According to one aspect of the pulse removal technique, a divider identification (DID) and a frequency ID (FID) may be employed to identify how a clock signal is to be modified for each P and C power management state, for example. Typically, a DID corresponds to a power of two division and an FID indicates how many pulses out of a maximum number of pulses are to remain in each pulse train. In this embodiment, the effective frequency is given by:

f _(e)=(f _(q)/DID)*(FID/P _(max))

where f_(e) is the effective frequency, f_(q) is the quadrature clock frequency, and P_(max) is the maximum number of pulses for the quadrature clock frequency. For example, if the quadrature clock frequency is 2.2 GHz, the maximum number of pulses is set to twenty-two. An effective frequency of 600 MHz may be achieved by setting DID equal to two and FID equal to twelve (f_(e)=(2.2 GHz/2)*(12/22)=600 MHz).

Example effective frequencies for different FID and DID values for a quadrature clock frequency of 2.0 GHz are set forth in TABLE 4 below.

TABLE 4 DID FID 1 2 4 8 16 128 512 11 1100 550 275 137.5 125 15.625 3.90625 12 1200 600 300 150 125 15.625 3.90625 13 1300 650 325 162.5 125 15.625 3.90625 14 1400 700 350 175 125 15.625 3.90625 15 1500 750 375 187.5 125 15.625 3.90625 16 1600 800 400 200 125 15.625 3.90625 17 1700 850 425 212.5 125 15.625 3.90625 18 1800 900 450 225 125 15.625 3.90625 19 1900 950 475 237.5 125 15.625 3.90625 20 2000 1000 500 250 125 15.625 3.90625 For TABLE 4, the maximum number of pulses is set to twenty. To provide a 1.5 GHz generated clock signal from the 2.0 GHz quadrature clock signal, the DID may be set to one and the FID may be set to fifteen (1.5 GHz=(2.0 GHz/1)*(15/20)), which corresponds to skipping five pulses out of every twenty pulses of a 2.0 GHz quadrature clock signal. With reference to TABLE 1, a 2.0 GHz clock signal may be generated using a pattern of “1100” (see FIG. 10) for each quadrature clock cycle (i.e., each four clock edges). To generate a 1.5 GHz clock signal out of twenty quadrature clock cycles, five of the twenty pulses may be removed using the following patterns for consecutive quadrature clock cycles as follows: “1100” for the first cycle; “1100” for the second cycle; “1100” for the third cycle; “0000” for the fourth cycle; “1100” for the fifth cycle; “1100” for the sixth cycle; “1100” for the seventh cycle; “0000” for the eighth cycle; “1100” for the ninth cycle; “1100” for the tenth cycle; “1100” for the eleventh cycle; “0000” for the twelfth cycle; “1100” for the thirteenth cycle; “1100” for the fourteenth cycle; “1100” for the fifteenth cycle; “0000” for the sixteenth cycle; “1100” for the seventeenth cycle; “1100” for the eighteenth cycle; “1100” for the nineteenth cycle; and “0000” for the twentieth cycle. It should be noted that the patterns in the fourth, eighth, twelfth, sixteenth, and twentieth cycles cause the pulses in those cycles to be removed from the clock stream. It should be appreciated the same effective frequency may be achieved by removing pulses from different cycles, other than the indicated cycles. The patterns may be generated by, for example, a state machine.

With reference to FIG. 11, a process 1100 for providing a generated clock signal is depicted. In block 1102, the process 100 is initiated at, for example, power-up of the processing system 400. Next, in block 1104, a reference clock signal is received by the PLL 402 of the processing system 400. Then, in block 1106, in response to the reference clock signal, the PLL 402 provides quadrature clock signals to one or more clock generators 404 and 406 of the processing system 400. Also, in block 1106, respective clock state machines (not shown in FIG. 4) provide appropriate respective mode signals (enable or mode bits) for the clock generators 404 and 406, based on respective frequencies selected for each of the clock generators 404 and 406. Then, in block 1108, the clock generators 404 and 406 receive the respective mode signals and the quadrature clock signals.

Next, in block 1110, the clock generators 404 and 406 provide respective generated clock signals to respective clocked logic circuits (in this case CPIJs 408 and 410), which in this case are static clocked logic circuits. Then, in decision block 1112, the respective clock state machines determine whether the power management module 412 has indicated that a power state changed is desired. If a power state change is not indicated in block 1112, control loops on block 1112. When a power state change is indicated in block 1112, control transfers to decision block 1114, where the state machines determine whether the processor system 400 is to be powered down. If power down is indicated in block 1114, control transfers to block 1118 where the process 1100 ends. Otherwise, when power down is not indicated in block 1114, control transfers to block 1116, where the state machines modify the respective mode signals based on information provided by the power management module 412.

In a processing system, it is common for different subsystems to operate at different frequencies. For example, a double data rate (DDR) memory module may be designed to operate at several set frequencies, e.g., multiples of 100 MHz. In a typical processing system, achieving the different frequencies from a PLL associated with a CPU core usually requires an integer (e.g., 1, 2, 3, etc.) divider or an integer plus one-half (e.g., 1.5, 2.5, etc.) divider. In this case, as the DDR frequency depends on a maximum CPU core frequency, the DDR frequency may not be an ideal frequency, but the nominal difference is usually less than or equal to ten percent from the ideal frequency and is satisfactory for most applications.

For example, assuming that a PLL is providing quadrature clock signals at 2.3 GHz and a CPU is initially operating at 2.3 GHz (i.e., DID is set equal to one and an FID is set equal to twenty-three) and a power management state change indicates that a 700 MHZ frequency is desired for the CPU. In this case, a clock generator associated with the CPU receives a pattern (from an associated state machine) corresponding to a DID of two and an FID of fourteen. Similarly, a default Northbridge clock signal having a 200 MHz frequency can be derived from the 2.3 GHz clock signal by providing a pattern to an associated clock generator that corresponds to a divide by 11.5. Moreover, a 383 MHz clock signal may be derived from the 2.3 GHz clock signal for a memory module (e.g., a DDR2-800 memory module) by providing a pattern that causes an associated clock generator to implement a divide by 6. While the clock signal is not an ideal 400 MHz clock signal, as noted above, the clock signal is within ten percent of the desired value.

TABLE 5 set forth below illustrates a number of exemplary frequencies that may be derived from a number of different quadrature clock signal frequencies (800 to 3200 MHz) using the techniques disclosed herein.

TABLE 5 NCLK NCLK2x NCLK2x Freq NCLK (50—50) Freq tCycle NCLK2x NCLK2x duty cycle = tH/ (MHz) Div *2 Freq (MHz) (MHz) (ps) tH (ps) tL (ps) tCycle * 100 800 4 400.00 800.00 1250 625 625 50.00 900 5 360.00 720.00 1389 556 833 40.00 1000 5 400.00 800.00 1250 500 750 40.00 1100 6 366.67 733.33 1364 682 682 50.00 1200 6 400.00 800.00 1250 625 625 50.00 1300 7 371.43 742.86 1346 577 769 42.86 1400 7 400.00 800.00 1250 536 714 42.86 1500 8 375.00 750.00 1333 667 667 50.00 1600 8 400.00 800.00 1250 625 625 50.00 1700 9 377.78 755.56 1324 588 735 44.44 1800 9 400.00 800.00 1250 556 694 44.44 1900 10 380.00 760.00 1316 658 658 50.00 2000 10 400.00 800.00 1250 625 625 50.00 2100 11 381.82 763.64 1310 595 714 45.45 2200 11 400.00 800.00 1250 568 682 45.45 2300 12 383.33 766.67 1304 652 652 50.00 2400 12 400.00 800.00 1250 625 625 50.00 2500 13 384.62 769.23 1300 600 700 46.15 2600 13 400.00 800.00 1250 577 673 46.15 2700 14 385.71 771.43 1296 648 648 50.00 2800 14 400.00 800.00 1250 625 625 50.00 2900 15 386.67 773.33 1293 603 690 46.67 3000 15 400.00 800.00 1250 583 667 46.67 3100 16 387.50 775.00 1290 645 645 50.00 3200 16 400.00 800.00 1250 625 625 50.00 In TABLE 5, the target DDR frequency is 400 MHz. As can be seen from reviewing the data in the table the NCLK frequency varies between 360 and 400 MHz and the NCLK2x frequency varies between 720 and 800 MHz.

According to another aspect of the present disclosure, a technique is disclosed that facilitates the manipulation of a specified generated clock signal cycle during functional and speed test of an integrated circuit (IC), without having to relock an associated PLL. That is, the technique facilitates stopping, shrinking, and stretching of one or more specified generated clock signal cycles based on a user (e.g., test engineer) specified clock requirement. The technique provides fine grain resolution which allows for determining which generated clock signal cycle(s) in a given speed path experience a problem. Advantageously, the technique reduces IC debug time and improves debug accuracy. For example, a low-phase or a high-phase of one or more generated clock signal cycles may be shrunk, stretched, or omitted during a functional or speed test of various paths in the IC. In a typical functional or speed test, a known set of instructions is executed by a CPU. According to one or more aspects of the present disclosure, when a failure occurs, a test engineer can provide a test pattern that allows for the determination of which specific generated clock signal cycle or cycles (and which corresponding path or paths) are associated with the failure. Moreover, the test engineer can provide a test pattern that facilitates the determination of a highest clock frequency (speed) for a specified path in an IC.

In one embodiment, as noted above, generated clock signals (e.g., GCLK0 or GCLK1) are based on quadrature clock signals (CLK_0 and CLK_90) and a mode signal (enable bits) that is generated by a state machine using a divide-by-eight clock signal (DIV8_CLK) that is derived from the CLK_0 signal. According to various aspects of the present disclosure, a generated clock signal can be shrunk or stretched by employing an appropriate set of mode signals (enable bits). In one embodiment, a pair of enable bits (one enable bit for a high-phase and one enable bit for a low-phase) may be used to completely describe one quadrature clock cycle. It should be appreciated that the reference clock signal (REFCLK), which is provided to a reference clock input of a PLL that provides the quadrature clock signals, may not always be aligned with the DIV8_CLK signal, which depends on a value a feedback divider (multiplier) of the PLL. In one disclosed embodiment, the generation of the mode signal is in the DIV8_CLK signal clock domain. In this case, the DIV8_CLK signal is not visible or directly externally controllable (e.g., with a tester). According to one embodiment, a test engineer provides an external trigger to facilitate modification of a generated clock signal cycle of interest. In the case of the implementation of an internal divide-by-eight in the clock generator, the external trigger is provided sixteen REFCLK cycles prior to a target REFCLK cycle. It should be appreciated that in the event that clock generator employs a different divider, the relationship of the external trigger to a target REFCLK cycle would change.

To implement shrinking according to one embodiment, two sets of (f*2) enable bits (one of which describes a generated clock signal for ‘f’ quadrature clock cycles within a target REFCLK cycle and another of which describes the generated clock signal for ‘f’ quadrature clock cycles within a dummy REFCLK cycle that follows the target REFCLK cycle) may be utilized. As used herein, ‘f’ is the value for the PLL feedback divider (multiplier). To implement stretching according to one embodiment, a set of (f*2) enable bits is used to describe a generated clock signal for ‘f’ quadrature clock cycles within a target RFFCLK cycle and another set (f*2) enable bits is used to describe the generated clock signal for ‘f’ quadrature clock cycles of a dummy REFCLK cycle. As one example, for ‘f’ equal to eight, thirty-two enable bits (10 10 10 10 10 10 10 10 (×2)) are implemented to provide a generated clock signal that is a divide-by-one of the CLK_0 signal. As another example, for ‘f’ equal to thirteen, fifty-two enable bits (10 10 10 10 10 10 10 10 10 10 10 10 (×2)) are implemented to provide a generated clock signal that is a divide-by-one of the CLK_0 signal.

For a given target REFCLK cycle, the corresponding DIV8_CLK cycle is determined and a set of enable bits is provided. As the DIV8_CLK signal is a divided version of CLK_0 signal, there will always be an edge alignment of DIV8_CLK signal and REFCLK signal every eight REFCLK cycles. In this case, there are ‘f’ DIV8_CLK. cycles within each eight REFCLK cycles (see FIG. 12). The target DIV8_CLK cycle is calculated based on the following equation:

target DIV8_CLK cycle=(target REFCLK cycle*f)/8

In the above equation, the target DIV8_CLK cycle takes on the value of the quotient (i.e., integer part) of the division on the left hand side of the equation. For example, assuming ‘f’ is equal to fifteen and the target REFCLK cycle is equal to three, the target DIV8_CLK is equal to five. Alternatively, a ceiling can be applied to the right hand side of the equation. With reference to FIG. 12, an example timing diagram 1200 illustrates how an external trigger is used to trigger a stretch or a shrink in a target REFCLK cycle (the dummy REFCLK cycle is not shown in FIG. 12). In one or more embodiments, the enable bits to describe the generated clock signal cycles after the target REFCLK cycle are generated such that the alignment of DIV8_CLK and the quadrature clock cycle boundaries are preserved. In one embodiment, a set of internally generated clock enables are provided to generate the required generated clock signals for a range of PLL multipliers from 8 to 40.

Shrinking a particular generated clock signal cycle is achieved by manipulating the enable bits provided in a mode signal. In the examples given in FIGS. 13-15, enable bits associated with a target REFCLK cycle are used to modify a desired GCLK cycle within a target REFCLK cycle. In the cases shown in FIGS. 13-15, ‘f’ is set equal to 9 and DID is set equal to two and two DIV8_CLK cycles worth of enable bits are utilized to manipulate selected GCLK cycles. In this case, each of the illustrated bits, i.e., ‘1’ or ‘0’, corresponds to two bits when expanded in the clock generator. For ‘f’ equal to nine and DID equal to two, two DIV8_CLK cycles encompass the target REFCLK. cycle (see FIG. 12). In signal diagram 1300 of FIG. 13, an original pattern 1302 is modified to provide a modified pattern 1304. The modified pattern 1304 includes a GCLK high-phase that is shrunk and a GCLK low-phase that is stretched to maintain the same number of GCLK cycles between the original pattern 1302 and the modified pattern 1304. This facilitates determination of whether high-phase hold-times on paths associated with the modified GCLK cycle are sufficient.

In signal diagram 1400 of FIG. 14, an original pattern 1402 is modified to provide a modified pattern 1404. The modified pattern 1404 includes a GCLK high-phase that is shrunk, a GCLK low-phase that is changed to a GCLK high-phase and a subsequent GCLK high-phase that is changed to a GCLK low-phase to effectively maintain the same number of GCLK cycles between the original pattern 1402 and the modified pattern 1404. This effectively doubles the frequency in one GCLK cycle and facilitates speed path testing of paths associated with the modified GCLK cycle. In the example shown in FIG. 15, the shrink of a GCLK low-phase and stretch of the GCLK high-phase maintain a same number of GCLK cycles. In signal diagram 1500 of FIG. 15, an original pattern 1502 is modified to provide a modified pattern 1504. The modified pattern 1504 includes a GCLK high-phase that is stretched and a GCLK low-phase that is shrunk to maintain the same number of GCLK cycles between the original pattern 1502 and the modified pattern 1504.

According to another aspect of the present disclosure, a stop mode is implemented to cause all zeros to be provided, within a target REFCLK cycle, following a selected GCLK cycle. The stop mode may be implemented through a stop-on-a-dime bit which, when set, causes a clock generator state machine to provide enable bits until a target REFCLK cycle (indicated by an external trigger) is encountered. Subsequent to the target REFCLK cycle, the clock generator state machine generates all zero enable bits, which stops the generated clock signals. A state of a processor may then be read out, via a scan, for analysis.

With reference to FIG. 16, a block diagram 1600 depicts a relevant portion of a debug interface 1602 (e.g., a joint test action group (JTAG) module) coupled to a clock generator 1610, which may be configured in a similar manner as the clock generator 600 of FIG. 6. The debug interface 1602 receives a number of input signals provided by, for example, a test engineer via a tester. The input signals include a reset signal (TRST), a clock signal (TCLK), a number of control signals (TCTLS), and a data-in signal (TDI) which are standard JTAG signals. The interface 1602 also receives an edge aligned signal that indicates when edges of the REFCLK signal and the DIV8_CLK signal are aligned. The interface 1602 receives two clock signals (REFCLK and DIV8_CLK), which are described above, in addition to respective reset signals (REFCLK RST and DIV8_CLK RST) associated with the clock signals.

The debug interface 1602 includes a number of modules 1604, 1606, and 1608, which provide various functionality. The module 1604 provides a test data register (TDR) for functional speed debugging. The TDR of the module 1604 may include, for example: a one-bit register (EN) that indicates whether speed debug is enabled; a two-bit register (CSEL) that indicates which cores are selected for speed debug; a one-bit register (SOAD) that indicates whether a clock is to be stopped after a selected quadrature clock cycle; and a 160-bit register (CLKEN) that stores enable bits provided by a test engineer. The module 1606 provides a PLL select TDR that, among other registers, includes: a six-bit register (CFBPDIV) that is used to indicate a PLL multiplier value; a three-bit register (CVCDID) that is used to indicate a DID value; and a one-bit register (CPSEL) that, when asserted, provides a core PLL enable. The modules 1604 and 1606 provide various signals to the module 1608, which the module 1608 uses for various purposes. The module 1608 performs clock alignment detection for the REFCLK and DIV8_CLK signals using the edge aligned signal. The module 1608 may also perform enable bit generation, enable bit padding, and internal trigger generation. As is illustrated, the interface 1602 provides enable bits (ENABLES), an internal trigger, and a configuration signal, which indicates a mode of operation (e.g., stretch, shrink, stop-on-a-dime), to the clock generator 1610.

The number of enable bits provided for stretching or shrinking is aligned to the quadrature clock cycles in the target REFCLK cycle. The generated clock signal cycles prior to the target REFCLK cycle (but within the DIV8_CLK cycle, which extends into the target REFCLK cycle) are generated by taking into account the DID (e.g., if the DID is one the pattern would be ‘1010’ or if the DID is two the pattern would be ‘1100’). The number of higher-order enable bits to be added to the test engineer provided enable bits is calculated by the following equation:

higher-order bits to be added=((target REFCLK*f)−(Target DIV8_CLK*8))*2

Accordingly, a number of techniques have been described herein that facilitate functional and speed test of an integrated circuit.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof. 

1. A method, comprising: receiving a test pattern; providing a mode signal based on the test pattern; receiving a first clock signal, a second clock signal, and the mode signal, wherein the first and second clock signals are out of phase and have the same clock frequency; and providing a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
 2. The method of claim 1, further comprising: providing the generated clock signal with a selected high-phase shrunk, wherein the selected high-phase is based on the mode signal.
 3. The method of claim 1, further comprising: providing the generated clock signal with a selected low-phase shrunk, wherein the selected low-phase is based on the mode signal.
 4. The method of claim 1, further comprising: providing the generated clock signal with a selected high-phase shrunk and a selected low-phase shrunk, wherein the selected high-phase and the selected low-phase are based on the mode signal.
 5. The method of claim 4, wherein the mode signal causes another low-phase of the generated clock signal to be stretched following the selected high-phase and the selected low-phase.
 6. The method of claim 1, wherein the second clock signal is a quadrature version of the first clock signal.
 7. The method of claim 1, wherein the mode signal is configured to provide a respective enable bit for each two consecutive edges of the first and second clock signals.
 8. The method of claim 1, wherein the mode signal sets the effective frequency of the generated clock signal to one-half the clock frequency of the first clock signal.
 9. The method of claim 1, further comprising: stopping the generated clock signal following a selected quadrature clock cycle, wherein the selected quadrature clock cycle is based on the mode signal.
 10. An integrated circuit, comprising: a debug module configured to receive a test pattern, wherein the debug module is configured to provide a mode signal based on the test pattern; and a clock generator including a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal, wherein the first and second clock signals are out of phase and have the same clock frequency, and wherein the clock generator is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
 11. The integrated circuit of claim 10, wherein the mode signal is configured to cause a selected high-phase of the generated clock signal to be shrunk.
 12. The integrated circuit of claim 10, wherein the mode signal is configured to cause a selected low-phase of the generated clock signal to be shrunk.
 13. The integrated circuit of claim 10, wherein the mode signal is configured to cause a selected high-phase of the generated clock signal to be shrunk and a selected low-phase of the generated clock signal to be shrunk.
 14. The integrated circuit of claim 13, wherein the mode signal is further configured to cause another low-phase of the generated clock signal to be stretched following the selected high-phase and the selected low-phase.
 15. The integrated circuit of claim 10, wherein the second clock signal is a quadrature version of the first clock signal.
 16. The integrated circuit of claim 10, wherein the mode signal is configured to provide a respective enable bit for each two consecutive edges of the first and second clock signals, and wherein the mode signal is configured to set the effective frequency of the generated clock signal to one-half the clock frequency.
 17. The integrated circuit of claim 10, wherein the mode signal is configured to cause the generated clock signal to stop following a selected quadrature clock cycle.
 18. A processor, comprising: a central processing unit having a clock input; a register configured to receive a test pattern; a mode signal generator coupled to the register, wherein the mode signal generator is configured to provide a mode signal, based on the test pattern; and a clock generator configured to receive a first clock signal, a second clock signal, and the mode signal, wherein the first and second clock signals are out of phase and have the same clock frequency and the clock generator is configured to provide a generated clock signal to the clock input of the central processing unit, and wherein the generated clock signal has an effective frequency that is based on the first and second clock signals and the mode signal, where the mode signal is configured to cause at least one of a selected high-phase and a selected low-phase of the generated clock signal to be shrunk.
 19. The processor of claim 18, wherein the mode signal is configured to cause both the selected high-phase and the selected low-phase of the generated clock signal to be shrunk and a subsequent low-phase of the generated clock signal to be stretched, and wherein the mode signal is configured to set the effective frequency of the generated clock signal to one-half the clock frequency of the first clock signal.
 20. The processor of claim 18, wherein the mode signal is configured to cause the generated clock signal to stop following a selected quadrature clock cycle. 